PIC24FJ128GB204用のアプリの作成（１）

MCCでソースコードを作ります。

コンフィグレーションはUSBブートローダと同じにする必要があります。

設定でデフォルトから変更するのは次の通りです。

Generateボタンを押します。

出来上がったCWは以下の通りです。

// CONFIG4
#pragma config DSWDTPS = DSWDTPS1F // Deep Sleep Watchdog Timer Postscale Select bits->1:68719476736 (25.7 Days)
#pragma config DSWDTOSC = LPRC // DSWDT Reference Clock Select->DSWDT uses LPRC as reference clock
#pragma config DSBOREN = ON // Deep Sleep BOR Enable bit->DSBOR Enabled
#pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable->DSWDT Enabled
#pragma config DSSWEN = ON // DSEN Bit Enable->Deep Sleep is controlled by the register bit DSEN
#pragma config PLLDIV = DIVIDE2 // USB 96 MHz PLL Prescaler Select bits->Oscillator input divided by 2 (8 MHz input)
#pragma config I2C1SEL = DISABLE // Alternate I2C1 enable bit->I2C1 uses SCL1 and SDA1 pins
#pragma config IOL1WAY = ON // PPS IOLOCK Set Only Once Enable bit->Once set, the IOLOCK bit cannot be cleared

// CONFIG3
#pragma config WPFP = WPFP127 // Write Protection Flash Page Segment Boundary->Page 127 (0x1FC00)
#pragma config SOSCSEL = OFF // SOSC Selection bits->Digital (SCLKI) mode
#pragma config WDTWIN = PS25_0 // Window Mode Watchdog Timer Window Width Select->Watch Dog Timer Window Width is 25 percent
#pragma config PLLSS = PLL_FRC // PLL Secondary Selection Configuration bit->PLL is fed by the on-chip Fast RC (FRC) oscillator
#pragma config BOREN = ON // Brown-out Reset Enable->Brown-out Reset Enable
#pragma config WPDIS = WPDIS // Segment Write Protection Disable->Disabled
#pragma config WPCFG = WPCFGDIS // Write Protect Configuration Page Select->Disabled
#pragma config WPEND = WPENDMEM // Segment Write Protection End Page Select->Write Protect from WPFP to the last page of memory

// CONFIG2
#pragma config POSCMD = NONE // Primary Oscillator Select->Primary Oscillator Disabled
#pragma config WDTCLK = LPRC // WDT Clock Source Select bits->WDT uses LPRC
#pragma config OSCIOFCN = ON // OSCO Pin Configuration->OSCO/CLKO/RA3 functions as port I/O (RA3)
#pragma config FCKSM = CSDCMD // Clock Switching and Fail-Safe Clock Monitor Configuration bits->Clock switching and Fail-Safe Clock Monitor are disabled
#pragma config FNOSC = FRCPLL // Initial Oscillator Select->Fast RC Oscillator with PLL module (FRCPLL)
#pragma config ALTRB6 = APPEND // Alternate RB6 pin function enable bit->Append the RP6/ASCL1/PMPD6 functions of RB6 to RA1 pin functions
#pragma config ALTCMPI = CxINC_RB // Alternate Comparator Input bit->C1INC is on RB13, C2INC is on RB9 and C3INC is on RA0
#pragma config WDTCMX = WDTCLK // WDT Clock Source Select bits->WDT clock source is determined by the WDTCLK Configuration bits
#pragma config IESO = ON // Internal External Switchover->Enabled

// CONFIG1
#pragma config WDTPS = PS1 // Watchdog Timer Postscaler Select->1:1
#pragma config FWPSA = PR32 // WDT Prescaler Ratio Select->1:32
#pragma config WINDIS = OFF // Windowed WDT Disable->Standard Watchdog Timer
#pragma config FWDTEN = OFF // Watchdog Timer Enable->WDT disabled in hardware; SWDTEN bit disabled
#pragma config ICS = PGx1 // Emulator Pin Placement Select bits->Emulator functions are shared with PGEC1/PGED1
#pragma config LPCFG = OFF // Low power regulator control->Disabled - regardless of RETEN
#pragma config GWRP = OFF // General Segment Write Protect->Write to program memory allowed
#pragma config GCP = OFF // General Segment Code Protect->Code protection is disabled
#pragma config JTAGEN = OFF // JTAG Port Enable->Disabled

※CONFIG2のFNOSC = FRC は FRCPLLに手直しが必要になりました（数か月前はうまくいっていたのに原因不明です）

#pragma config FNOSC = FRCPLL  //ハンド修正

次の記事は、http://fujiharagiken.hatenablog.com/entry/2018/05/18/213844